This relates to the structure and operation of re-programmable non-volatile memories, particularly to the programming of flash semiconductor memory cells by an improved substrate hot electron injection technique. All patents, patent applications, articles and other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small memory cards and flash memory drives. Individual memory cells of an array are formed on a semiconductor wafer with conductive floating gates, most commonly made of doped polysilicon material, on which an electron charge is stored to a level according to the data being stored in the cell. The floating gate is positioned over at least a portion of a channel between source and drain regions, with a gate dielectric between the floating gate and the substrate. The threshold voltage of the memory cell is controlled by the amount of charge on the floating gate.
There are two classes of memory cell arrays that are currently the most common, NOR and NAND, which differ primarily in the manner in which the memory cells are connected together. In a NOR array, drain connections of the individual cells are connected together in parallel to common bit lines. Examples of NOR memory cell arrays, their uses in memory systems and methods of manufacturing them are given in United States U.S. Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, and 5,661,053, and 6,281,075.
In the NAND configuration, eight, sixteen or more memory cells are connected in series with each other in strings that are selectively connected between individual bit lines and a common potential by select transistors at each end of the strings. Word lines extend across memory cells of multiple strings. Examples of NAND flash memory cell arrays and their operation as part of a memory system may be had by reference to U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935, 6,373,746, 6,456,528, 6,522,580, 6,771,536 and 6,781,877 and United States patent application publication no. 2003/0147278A1.
There are various programming techniques for causing electrons from the substrate to travel through the gate dielectric and onto the floating gate. The most common programming mechanisms are described in a book edited by Brown and Brewer, “Nonvolatile Semiconductor Memory Technology,” IEEE Press, section 1.2, pages 9-25 (1998). One technique, termed “Fowler-Nordheim tunneling” (section 1.2.1), causes electrons to tunnel through the floating gate dielectric under the influence of a high field that is established thereacross by a voltage difference between the control gate and the substrate channel. Another technique, channel hot electron injection in the drain region, commonly referred to as “hot-electron injection” (section 1.2.3), injects electrons from the cell's channel into a region of the floating gate adjacent the cell's drain. Yet another technique, termed “source side injection” (section 1.2.4), controls the substrate surface electrical potential along the length of the memory cell channel in a manner to create conditions for electron injection in a region of the channel away from the drain. Source side injection is also described in an article by Kamiya et al., “EPROM Cell with High Gate Injection Efficiency,” IEDM Technical Digest, 1982, pages 741-744, and in U.S. Pat. Nos. 4,622,656 and 5,313,421. In a further programming technique, termed “ballistic injection”, high fields are generated within a short channel to accelerate electrons directly onto the charge storage element, as described by Ogura et al., “Low Voltage, Low Current, High Speed Program Step Split Gate Cell with Ballistic Direct Injection for EEPROM/Flash”, IEDM 1998, pages 987-990.
Yet another programming technique, termed “substrate hot electron injection,” causes electrons that enter a depletion region under the channel to be accelerated by an electric field to the substrate surface and then through the gate dielectric to the floating gate. An early description of this programming mechanism is found in an article by Eitan et al., “Substrate Hot-Electron Injection EPROM,” IEEE Transactions on Electron Devices, vol. ED-31, no. 7, pp. 934-942 (July 1984). Many different techniques have been proposed for the generation of enough electrons in the substrate for efficient programming. Eitan et al. add a bipolar device on the surface of the substrate adjacent an electrically programmable read-only-memory (EPROM) cell being programmed. Another approach is to form a buried injector in the substrate under the channel of the memory cell that emits electrons into the depletion layer when its p-n junction is subjected to punchthrough conditions. See, for example, Wijburg et al., “VIPMOS—A Novel Buried Injector Structure for EPROM Applications,” IEEE Transactions on Electron Devices, vol. 38, no. 1, pp. 111-120 (January 1991), and U.S. Pat. No. 5,216,269.
There are two common erase techniques that remove charge from floating gates of flash electrically erasable and programmable read-only-memory (EEPROM) cells. One is to erase floating gates to the substrate by applying appropriate voltages to the source, drain, substrate and other gate(s) that cause electrons to tunnel through a portion of a dielectric layer between the floating gate and the substrate. The other erase technique transfers electrons from the floating gate to another gate through a thin tunnel dielectric layer positioned between them.
It is continuously desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell floating gate. This is accomplished by dividing a window of charge storage into more than two levels or ranges. The use of four such states allows each cell to store two bits of data, a cell with sixteen states stores four bits of data, and so on. Multiple state flash EEPROM structures and their operation are described in U.S. Pat. Nos. 5,043,940, 5,172,338 and aforementioned U.S. Pat. No. 6,522,580, as examples.
Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to store charge in a non-volatile manner. One form of dielectric storage material is a triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (ONO). The dielectric is typically sandwiched between a conductive control gate and the semiconductor substrate above the memory cell channel. Various NOR and NAND arrays using dielectric charge storage are described in United States patent application publication no. 2003/0109093A1. Transferring electrons from the cell channel into the nitride, where they are trapped and stored in a limited area, programs dielectric storage cells.
Another alternative to floating gate memories and to dielectric storage memories is a technique of embedding very small conducting regions within the gate oxide to store trapped electrons, commonly called nanocrystal memories. As described in U.S. Pat. Nos. 6,656,792 and 6,090,666 and United States patent application publication no. 2004/0130941, these nano-crystalline sites are deposited in place of a conductive floating gate, being separated from the substrate by a tunneling oxide and being separated from the control gate by another insulator. The nanocrystals can be of a variety of materials including silicon, germanium, or various metals. They are typically of such small sizes and spatially isolated from each other such that there are a multitude of these nanocrystal regions covering the entire conductive channel region between source and drain.
The various programming techniques mentioned above may also be used with memory cells employing non-conductive dielectric charge-trapping devices or nanocrystals in place of conductive floating gates. Common erase techniques are also be used.